Staff Engineer, Digital design engineering (31)

FPGA Design And Implementation Engineer

Analog Devices, Inc. (NASDAQ: ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combatclimate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible.

Analog Devices is seeking an FPGA Design and Implementation Engineer.In this role, you will be responsible for building and maintaining FPGA-based prototyping platforms that enable early software development, RTL validation and system integration for complex SoC ASIC designs.You will own the complete FPGA build flow — from ingesting ASIC RTL, through synthesis and implementation, including timing closure and delivering working FPGA images to validation/software teams.

You will work closely with digital design, firmware, and silicon validation engineers to ensure seamless ASIC-to-FPGA translation, debug RTL issues on proFPGA multi-FPGA boards and drive continuous improvement of build infrastructure through automation.This is a hands-on role requiring deep expertise in Vivado tooling, clock architecture design, FPGA timing closure and the ability to bridge the gap between ASIC design intent and FPGA implementation constraints.

You will work as part of an international team, specialized in FPGA prototyping. The work location will be our state-of-the-art facility in Bangalore with the option of home office work (for suitable projects). The company has a goal of building up an FPGA team in Bangalore, where the close proximity to the design and verification departments is an added benefit. You are also encouraged to participate in cross company technical initiatives as well as patent and publishing work where possible.

Responsibilities

• Develop and maintain FPGA prototyping platforms for ASIC designs on Xilinx UltraScale+ (VU19P) and Siemens proFPGA multi-FPGA systems
• Own the FPGA synthesis, implementation, and timing closure flow using Vivado
• Port ASIC RTL to FPGA: clock tree adaptation, memory model replacement, IP stub creation, constraint development
• Develop and maintain automated build scripts (TCL, Python) for compile ordering, file management, and normal/incremental Vivado builds
• Debug synthesis/implementation failures, resolve timing violations, and optimize QoR (clock skew, utilization, routing congestion)
• Collaborate with ASIC design teams to integrate new RTL drops and resolve ASIC-to-FPGA porting issues
• Interface with FPGA vendor (AMD/Xilinx) on tool issues, file CRs, and drive resolutions
• Develop clock management architectures (PLL/MMCM cascading, clock muxing, clock disciplining, gated clock conversion)
• Support silicon validation and firmware teams with FPGA images and debug infrastructure
• Develop and execute bare-metal test programs (embedded C) for FPGA-based validation

Requirements

• 7+ years of FPGA design experience
• Expert-level Vivado experience (synthesis, implementation, timing constraints, incremental compile)
• Experience with ASIC-to-FPGA prototyping (RTL porting, memory replacement, clock adaptation)
• Deep understanding of FPGA clocking (MMCM, PLL, BUFG, BUFGCTRL, BUFGCE_DIV, clock muxing)
• Experience with timing closure on large designs (100K+ LUTs)
• Familiarity with XDC constraint development (clock definitions, false paths, multicycle paths, clock groups)

Optional Qualifications

• Hardware lab experience (board bring-up, oscilloscope/logic analyzer debug, JTAG probing, signal integrity)
• Experience with embedded C / bare-metal firmware development and testing on ARM platforms
• Familiarity with Intel/Quartus FPGA flows
• Experience with ASIC design flows (VCS, Xcelium, Synopsys DC)
• Knowledge of AXI/AHB/APB bus protocols
• Familiarity with ARM Cortex-M processor subsystems
• Experience with debug infrastructure (JTAG, CoreSight, ILA)
• Experience in using Git version control

Minimum Qualifications

• BS/BE in Electrical Engineering, Computer Science or Computer Engineering with some industry experience
• MSC / PhD in Electrical Engineering, Computer Science or related field.

Additional Skills, Knowledge, and Abilities

• Clear communication skills to present and report status and progress.
• Willingness and ability to learn new skills such as software scripting and computer networking.
• Strong organizational skills and the ability to work with aggressive schedules.
• Self-motivated, thorough, autonomous, and driven to continually improve.
• Lead a team, assist fellow engineers and develop solid solutions for technical problems.

Tools & Technologies

• Vivado, Xilinx UltraScale+
• proFPGA multi-FPGA systems
• TCL, Python, SystemVerilog
• Embedded C, GCC ARM toolchain, bare-metal RTOS
• Oscilloscope, logic analyzer, JTAG debugger
• Questa sim/VCS/Xcelium (for simulation cross-reference)

For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.

Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

Job Req Type: Experienced Required Travel: Yes, 10% of the time Shift Type: 1st Shift/Days