Digital Design (RTL) Engineer
Location: Santa Clara, CA Remote work option allowed
Required: Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural document from requirements specifications Experience developing designs from scratch Experience applying linting and other (QC) quality checking and basic verification of designs. Experience supporting SoC designers in integration as needed Strong communication and collaboration skills
Preferred: Desirable but not essential experience: DMA, memory controller, MIPI DSI/CSI, data and control path pipeline design, interconnect and AMBA interfaces. Candidate with design automation, scripting experience (Python) is preferrable
Develop HW architecture from specification documents.Take complete responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.Develop and execute low power design (UPF/CPF).
Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties) Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA.Debugging and fixing functional break.Take ownership of tasks and drive tasks to closure.Synopsys/Cadence EDA Tools (Priority: 1) LEC (Priority: 2) STA/Constraints (Priority: 2)
Digital Design (RTL) Engineer
Location: Santa Clara, CA Remote work option allowed
Required: Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural document from requirements specifications Experience developing designs from scratch Experience applying linting and other (QC) quality checking and basic verification of designs. Experience supporting SoC designers in integration as needed Strong communication and collaboration skills
Preferred: Desirable but not essential experience: DMA, memory controller, MIPI DSI/CSI, data and control path pipeline design, interconnect and AMBA interfaces. Candidate with design automation, scripting experience (Python) is preferrable
Develop HW architecture from specification documents.Take complete responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.Develop and execute low power design (UPF/CPF).
Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties) Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA.Debugging and fixing functional break.Take ownership of tasks and drive tasks to closure.Synopsys/Cadence EDA Tools (Priority: 1) LEC (Priority: 2) STA/Constraints (Priority: 2)
