Senior ASIC Design Verification Engineer
We are looking for a Senior ASIC Design Verification Engineer with strong expertise in digital logic, processor architecture, verification methodologies, and system level debugging.
About Us
On the market since 2002; operational departments and development hubs worldwide.
Project Description
Our partner develops next gen AI accelerators at the intersection of semiconductors, photonics, and AI.The project focuses on verification of complex digital and mixed signal ASICs, including high speed interfaces and compute blocks, with an emphasis on building scalable SystemVerilog/UVM environments, constrained random and coverage driven methodologies, assertions, formal verification, and timing accurate simulations with SDF back annotation.The scope also covers PCIe, RISC V CPU subsystems, corner case analysis, block and system debug, plus FPGA prototyping and post silicon validation.
The role requires strong expertise in digital design, processor architecture, and verification methodologies, along with solid debugging and system-level thinking skills.
Verification & Tools Environment
- SystemVerilog, UVM (scalable verification environment development).
- Full ASIC verification flow (block-level → full-chip).
- High-speed interface verification (PCIe) and CPU subsystems (RISC-V). Simulation tools: Xcelium / VCS / Questa.
- Coverage-driven and formal verification (assertions, functional coverage).
- Netlist simulation with SDF back-annotation.
- FPGA prototyping and post-silicon validation.
- Debugging and system-level analysis of complex scenarios.
Requirements
- 4+ years of SystemVerilog (verification) experience.
- Hands-on UVM (testbenches, agents, scoreboards, coverage).
- ASIC/SoC verification (block and/or system level).
- Strong in: constrained random; assertions (SVA); functional coverage. Experience with simulators: Cadence Design Systems (Xcelium) / Synopsys (VCS) / Siemens EDA (Questa).
- RTL / testbench debugging.
- Solid digital design & CPU basics.
- Fluent English (Upper-intermediate and above).
- Location in time zone: GMT+1/+3.
Nice to Have
- PCIe or other high-speed interfaces
- RISC-V / CPU verification
- Full-chip verification
- Formal verification
- Netlist + SDF simulation
- FPGA bring-up / post-silicon
- Mixed-signal
Responsibilities
- Contributing to a next-generation AI accelerator at the intersection of electronics and photonics, including verification of novel architectures with high ambiguity.
- Building verification environments from scratch for mixed-signal ASICs, ensuring timing-accurate behavior (netlist + SDF), performing system-level verification of PCIe and RISC-V subsystems, and shaping verification strategy while debugging complex system-level scenarios in a startup environment.
We Offer
- Employment is based on a contract between Cyprus legal entity and a private entrepreneur without any reference to a specific location.
- Paid vacations (24 working days/year) and sick leave.
- Stable long-term workload (8 hours per day, 40 hours per week), flexible working hours, fully remote.
- Working on exciting projects in international team of professionals.
- Opportunities for learning and practicing new technologies. Internal training.
- Participating in inner meetups and permanent experience exchange with colleagues.
- Well-defined development processes and methodologies.
- Partial reimbursement of medical fees, massage or sports.
Recognize yourself? We are waiting for your CV!
Senior ASIC Design Verification Engineer
We are looking for a Senior ASIC Design Verification Engineer with strong expertise in digital logic, processor architecture, verification methodologies, and system level debugging.
About Us
On the market since 2002; operational departments and development hubs worldwide.
Project Description
Our partner develops next gen AI accelerators at the intersection of semiconductors, photonics, and AI.The project focuses on verification of complex digital and mixed signal ASICs, including high speed interfaces and compute blocks, with an emphasis on building scalable SystemVerilog/UVM environments, constrained random and coverage driven methodologies, assertions, formal verification, and timing accurate simulations with SDF back annotation.The scope also covers PCIe, RISC V CPU subsystems, corner case analysis, block and system debug, plus FPGA prototyping and post silicon validation.
The role requires strong expertise in digital design, processor architecture, and verification methodologies, along with solid debugging and system-level thinking skills.
Verification & Tools Environment
- SystemVerilog, UVM (scalable verification environment development).
- Full ASIC verification flow (block-level → full-chip).
- High-speed interface verification (PCIe) and CPU subsystems (RISC-V). Simulation tools: Xcelium / VCS / Questa.
- Coverage-driven and formal verification (assertions, functional coverage).
- Netlist simulation with SDF back-annotation.
- FPGA prototyping and post-silicon validation.
- Debugging and system-level analysis of complex scenarios.
Requirements
- 4+ years of SystemVerilog (verification) experience.
- Hands-on UVM (testbenches, agents, scoreboards, coverage).
- ASIC/SoC verification (block and/or system level).
- Strong in: constrained random; assertions (SVA); functional coverage. Experience with simulators: Cadence Design Systems (Xcelium) / Synopsys (VCS) / Siemens EDA (Questa).
- RTL / testbench debugging.
- Solid digital design & CPU basics.
- Fluent English (Upper-intermediate and above).
- Location in time zone: GMT+1/+3.
Nice to Have
- PCIe or other high-speed interfaces
- RISC-V / CPU verification
- Full-chip verification
- Formal verification
- Netlist + SDF simulation
- FPGA bring-up / post-silicon
- Mixed-signal
Responsibilities
- Contributing to a next-generation AI accelerator at the intersection of electronics and photonics, including verification of novel architectures with high ambiguity.
- Building verification environments from scratch for mixed-signal ASICs, ensuring timing-accurate behavior (netlist + SDF), performing system-level verification of PCIe and RISC-V subsystems, and shaping verification strategy while debugging complex system-level scenarios in a startup environment.
We Offer
- Employment is based on a contract between Cyprus legal entity and a private entrepreneur without any reference to a specific location.
- Paid vacations (24 working days/year) and sick leave.
- Stable long-term workload (8 hours per day, 40 hours per week), flexible working hours, fully remote.
- Working on exciting projects in international team of professionals.
- Opportunities for learning and practicing new technologies. Internal training.
- Participating in inner meetups and permanent experience exchange with colleagues.
- Well-defined development processes and methodologies.
- Partial reimbursement of medical fees, massage or sports.
Recognize yourself? We are waiting for your CV!
