SENIOR/LEAD ASIC ENGINEER (48)

Lead ASIC DFT Engineer

Location: Remote (Must align with PST) Pay Rate: $80–$90/hr (W2) Visa: USC, GC, EAD (No OPT/CPT)

Senior-level ASIC DFT expert responsible for end-to-end DFT architecture, implementation, verification, and silicon debug for complex ASIC/SoC designs.

Key Skills (Must Have)

• Scan, ATPG, MBIST, LBIST
• Timing Simulation, SDF, SDC
• Pattern Retargeting / Porting
• Diagnosis, DRCs
• Tools: TetraMax, DFTMax

Experience

10+ years in ASIC DFT (hands-on)

Responsibilities

• Lead DFT architecture, implementation & sign-off
• Drive scan insertion, scan chains & compression flows
• Own MBIST/LBIST integration and debug
• Perform silicon debug, failure analysis & root cause
• Develop DFT constraints (SDC) & timing analysis
• Support ATPG generation, simulation & coverage closure
• Work on JTAG, boundary scan, iJTAG
• Collaborate across RTL, PD, STA, validation teams
• Mentor junior engineers
• Develop automation scripts (TCL/Perl/Python)

Requirements

• Strong DFT fundamentals & fault models knowledge
• Expertise in scan, ATPG, MBIST, JTAG, debug
• Experience with Synopsys / Cadence / Siemens tools
• Post-silicon validation experience
• Large SoC & hierarchical DFT exposure

Preferred

• Tessent / SSN tools
• Yield analysis & manufacturing test optimization
• Multi-node ASIC experience