Asic Verification Engineer -ARM (18)

ASIC Verification Engineer – ARM

Location: Remote

Job Summary:

We are seeking an experienced ASIC Verification Engineer with strong hands-on expertise in ARM-based SoC/Subsystem verification. The role focuses on ensuring high-quality design and verification of ARM IP blocks contributing to next-generation wireless portable hardware.

Key Responsibilities:

• Ensure overall quality of designs contributing to product launches in wireless portable hardware.
• Focus on ARM IPs (Cortex-A v9 architecture CPU, Mali GPU, CSS600, CoreSight debug, etc.) and support architectural/design verification decisions.
• Own and develop verification of core IP blocks as an individual contributor.
• Manage end-to-end verification lifecycle including:
• Specification reviews
• Verification planning
• Test case development
• UVM environment development
• Coverage analysis
• Debugging
• Gate Level Simulation (GLS)
• Collaborate with cross-functional teams to refine requirements and improve design specifications.
• Provide debugging support and technical feedback across teams.
• Work with global verification teams to improve methodologies, processes, and overall design quality.

Mandatory Skills & Experience:

• 5+ years of hands-on experience in verification methodologies including:
• UVM / SystemVerilog
• Formal verification
• Constraint-random verification
• Assertions
• Coverage metrics & analysis
• Gate Level Simulation (GLS)
• Strong understanding of ARM IPs (Cortex-A v9 CPU, Mali GPU, CoreSight, CSS600 debug, etc.).
• Experience developing C-based test cases for ARM IP validation.
• Experience building and reusing UVM-based test environments at block and subsystem level.
• Ability to read and interpret RTL (SystemVerilog, Verilog, VHDL).
• Experience with version control systems and CI/CD workflows.
• Strong collaboration and independent working capability.
• Excellent communication, documentation, and process development skills.

Optional Skills:

• Advanced experience with UVM-based testbench development and reuse at subsystem level.
• RTL debugging and interpretation across SystemVerilog / Verilog / VHDL.
• Experience with CI/CD pipelines and version control systems.
• Strong interpersonal and cross-team collaboration skills.
• Strong technical documentation and communication abilities.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.