Bachelor's degree in electrical engineering with 3+ experience or master's degree in electrical engineering or related field with 2+ year experience. Experience in Logic design, validation, and testing, including but not limited to: Micro-architecture definition of design features, test plan creation and functional verification. Effective behavioural modelling and testing of circuits in Verilog and System Verilog, as well as logical equivalence verification between Schematic and Verilog models. UPF (Unified Power Format) creation using low power techniques and handling multiple power domain design. Knowledge of Clock Domain Crossing, Design for Test, Register Description Language. Experience in test bench creation to generate test patterns and vectors. Experience with FEV (Formal Equivalence Verification) and GLS (Gate Level Simulations)
Bachelor's degree in electrical engineering with 3+ experience or master's degree in electrical engineering or related field with 2+ year experience. Experience in Logic design, validation, and testing, including but not limited to: Micro-architecture definition of design features, test plan creation and functional verification. Effective behavioural modelling and testing of circuits in Verilog and System Verilog, as well as logical equivalence verification between Schematic and Verilog models. UPF (Unified Power Format) creation using low power techniques and handling multiple power domain design. Knowledge of Clock Domain Crossing, Design for Test, Register Description Language. Experience in test bench creation to generate test patterns and vectors. Experience with FEV (Formal Equivalence Verification) and GLS (Gate Level Simulations)
What You'll Do
Bachelor's degree in electrical engineering with 3+ experience or master's degree in electrical engineering or related field with 2+ year experience.
Experience in Logic design, validation, and testing, including but not limited to: Micro-architecture definition of design features, test plan creation and functional verification.
Effective behavioural modelling and testing of circuits in Verilog and System Verilog, as well as logical equivalence verification between Schematic and Verilog models.
UPF (Unified Power Format) creation using low power techniques and handling multiple power domain design.
