Senior ASIC DFT CDC Constraints Engineer
Tekfortune is a fast-growing consulting firm specialized in permanent, contract & project-based staffing services for world's leading organizations in a broad range of industries. In this quickly changing economic landscape, virtual recruiting andremote work are critical for the future of work. To support the active project demands and skills gaps, our staffing experts can help you find the best job for you. Role: Senior ASIC DFT CDC Constraints Engineer Location: Remote Duration: 6 months Required Skills: Senior ASIC DFT CDC Constraints Eng
Job Description: Senior Clock Domain Crossing (CDC) Contractor to support our engineering team. This is a critical, focused on maintaining design integrity during a transition period. The ideal candidate will serve as a subject matter expert in CDC analysis and ASIC Design-for-Test (DFT) constraints. Leading the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips
Design & implement robust and reusable RTL with CDC/RDC considerations
Spec comprehensive CDC/RDC check flows and work with CAD team to implement
Review and approve CDC/RDC constraints and waivers
Perform static glitch analysis
Improve design with prevention of static glitch harzad
Minimum Qualifications
Bachelor's or Master's degree on Electrical Engineering with at least 10 years of experience on ASIC chip design · RTL development skills and experiences · Solid understanding on CDC/RDC concepts and relevant design implementation · Experience on maintaining CDC/RDC flow and signing-off constraints and waivers · Solid understanding on static glitch harzads and experience on the relevant analysis on synthesis optimized gate netlists · Experiences on Static Timing Analysis · Experiences on VCS simulation SVA (SystemVerilog Assertions)
Senior ASIC DFT CDC Constraints Engineer
Tekfortune is a fast-growing consulting firm specialized in permanent, contract & project-based staffing services for world's leading organizations in a broad range of industries. In this quickly changing economic landscape, virtual recruiting andremote work are critical for the future of work. To support the active project demands and skills gaps, our staffing experts can help you find the best job for you. Role: Senior ASIC DFT CDC Constraints Engineer Location: Remote Duration: 6 months Required Skills: Senior ASIC DFT CDC Constraints Eng
Job Description: Senior Clock Domain Crossing (CDC) Contractor to support our engineering team. This is a critical, focused on maintaining design integrity during a transition period. The ideal candidate will serve as a subject matter expert in CDC analysis and ASIC Design-for-Test (DFT) constraints. Leading the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips
Design & implement robust and reusable RTL with CDC/RDC considerations
Spec comprehensive CDC/RDC check flows and work with CAD team to implement
Review and approve CDC/RDC constraints and waivers
Perform static glitch analysis
Improve design with prevention of static glitch harzad
Minimum Qualifications
Bachelor's or Master's degree on Electrical Engineering with at least 10 years of experience on ASIC chip design · RTL development skills and experiences · Solid understanding on CDC/RDC concepts and relevant design implementation · Experience on maintaining CDC/RDC flow and signing-off constraints and waivers · Solid understanding on static glitch harzads and experience on the relevant analysis on synthesis optimized gate netlists · Experiences on Static Timing Analysis · Experiences on VCS simulation SVA (SystemVerilog Assertions)
