Business Services & Consulting • all cities, MT 27
VP Hardware Engineering (27)
all cities, MT 27On-sitePosted 22 hours ago
Business Services & Consulting
About the Role
VP Hardware Engineering
Location: Remote - New York, NY or San Francisco, CA
A stealth-mode AI hardware startup is turning breakthrough research in low-latency large-language-model inference into purpose-built silicon. After proving the concept in software and FPGA, the company is racing toward first-generation ASIC silicon and needs a hands-on executive to lead the charge. As VP Hardware Engineering, you will own the entire chip program from architecture to post-silicon bring-up, while shaping a world-class engineering organization that can scale with explosive customer demand. If you thrive on building new technology, attracting top talent, and delivering audacious roadmaps at startup speed, this is your once-in-a-career seat at the table.
Key Responsibilities
Define the architectural vision for a data-center-class AI inference accelerator and translate it into a scalable ASIC implementation.
Chart the course from proof-of-concept FPGAs toward a commercially manufactured AI accelerator ASIC within aggressive time-to-market goals.
Own the full silicon lifecycle: RTL design, verification, physical design, tape-out, and post-silicon validation.
Build, mentor, and inspire a high-performance hardware engineering organization, spanning digital design, verification, physical implementation, packaging, and systems.
Partner closely with applied-AI and software teams on hardware-software co-design that maximizes tokens-per-second and minimizes latency for LLM workloads.
Establish relationships with foundries, EDA vendors, and manufacturing partners; drive technical diligence and risk reduction.
Represent hardware engineering in executive planning, customer briefings, and investor discussions.
What Success Looks Like
First-silicon win - Tape-out of the company's inaugural inference ASIC on schedule and on budget, meeting PPA targets.
Team built - A cohesive, mission-driven silicon organization with clear ownership, processes, and recruiting pipeline.
Customer impact - Demonstrated order-of-magnitude throughput improvements for early design-partner deployments.
Strategic voice - Tangible influence on company strategy, product roadmap, and go-to-market positioning.
Ideal Candidate Profile
10+ years designing high-performance custom silicon for compute-intensive workloads; at least one successful tape-out in a leadership role.
Mastery of SoC/ASIC architecture, RTL (SystemVerilog/VHDL), verification methodology, physical design, and DFT.
Deep familiarity with memory hierarchies, high-bandwidth interconnects (PCIe, CXL, or similar), and accelerator-class power-performance trade-offs.
Prior experience converting FPGA prototypes into production silicon is highly valued.
Proven ability to recruit, develop, and lead multidisciplinary engineering teams in fast-moving startup or new-business environments.
Excellent communication and executive-level storytelling skills; comfortable presenting complex trade-offs to non-technical stakeholders.
Compensation & Benefits
Competitive base salary, commensurate with experience and impact expectations.
Equity: Founder-level grant with significant upside tied to first-silicon and market-adoption milestones.
Comprehensive health, dental, vision, and life benefits.
Unlimited PTO, flexible remote work, and quarterly on-site team summits.
Sponsored attendance at top industry conferences and access to best-in-class EDA tooling.
About Blue Signal:
Blue Signal is an award-winning, executive search firm specializing in various specialties. Our recruiters have a proven track record of placing top-tier talent across industry verticals, with deep expertise in numerous professional services. Learn more at bit.ly/46Gs4yS
VP Hardware Engineering
Location: Remote - New York, NY or San Francisco, CA
A stealth-mode AI hardware startup is turning breakthrough research in low-latency large-language-model inference into purpose-built silicon. After proving the concept in software and FPGA, the company is racing toward first-generation ASIC silicon and needs a hands-on executive to lead the charge. As VP Hardware Engineering, you will own the entire chip program from architecture to post-silicon bring-up, while shaping a world-class engineering organization that can scale with explosive customer demand. If you thrive on building new technology, attracting top talent, and delivering audacious roadmaps at startup speed, this is your once-in-a-career seat at the table.
Key Responsibilities
Define the architectural vision for a data-center-class AI inference accelerator and translate it into a scalable ASIC implementation.
Chart the course from proof-of-concept FPGAs toward a commercially manufactured AI accelerator ASIC within aggressive time-to-market goals.
Own the full silicon lifecycle: RTL design, verification, physical design, tape-out, and post-silicon validation.
Build, mentor, and inspire a high-performance hardware engineering organization, spanning digital design, verification, physical implementation, packaging, and systems.
Partner closely with applied-AI and software teams on hardware-software co-design that maximizes tokens-per-second and minimizes latency for LLM workloads.
Establish relationships with foundries, EDA vendors, and manufacturing partners; drive technical diligence and risk reduction.
Represent hardware engineering in executive planning, customer briefings, and investor discussions.
What Success Looks Like
First-silicon win - Tape-out of the company's inaugural inference ASIC on schedule and on budget, meeting PPA targets.
Team built - A cohesive, mission-driven silicon organization with clear ownership, processes, and recruiting pipeline.
Customer impact - Demonstrated order-of-magnitude throughput improvements for early design-partner deployments.
Strategic voice - Tangible influence on company strategy, product roadmap, and go-to-market positioning.
Ideal Candidate Profile
10+ years designing high-performance custom silicon for compute-intensive workloads; at least one successful tape-out in a leadership role.
Mastery of SoC/ASIC architecture, RTL (SystemVerilog/VHDL), verification methodology, physical design, and DFT.
Deep familiarity with memory hierarchies, high-bandwidth interconnects (PCIe, CXL, or similar), and accelerator-class power-performance trade-offs.
Prior experience converting FPGA prototypes into production silicon is highly valued.
Proven ability to recruit, develop, and lead multidisciplinary engineering teams in fast-moving startup or new-business environments.
Excellent communication and executive-level storytelling skills; comfortable presenting complex trade-offs to non-technical stakeholders.
Compensation & Benefits
Competitive base salary, commensurate with experience and impact expectations.
Equity: Founder-level grant with significant upside tied to first-silicon and market-adoption milestones.
Comprehensive health, dental, vision, and life benefits.
Unlimited PTO, flexible remote work, and quarterly on-site team summits.
Sponsored attendance at top industry conferences and access to best-in-class EDA tooling.
About Blue Signal:
Blue Signal is an award-winning, executive search firm specializing in various specialties. Our recruiters have a proven track record of placing top-tier talent across industry verticals, with deep expertise in numerous professional services. Learn more at bit.ly/46Gs4yS
What You'll Do
Define the architectural vision for a data-center-class AI inference accelerator and translate it into a scalable ASIC implementation.
Chart the course from proof-of-concept FPGAs toward a commercially manufactured AI accelerator ASIC within aggressive time-to-market goals.
Own the full silicon lifecycle: RTL design, verification, physical design, tape-out, and post-silicon validation.
Build, mentor, and inspire a high-performance hardware engineering organization, spanning digital design, verification, physical implementation, packaging, and systems.
Partner closely with applied-AI and software teams on hardware-software co-design that maximizes tokens-per-second and minimizes latency for LLM workloads.
Establish relationships with foundries, EDA vendors, and manufacturing partners; drive technical diligence and risk reduction.
